Title

Hardware architecture for popcount

Document Type

Article

Source of Publication

WSEAS Transactions on Computers

Publication Date

7-1-2006

Abstract

Bit-counting implementations are used to count the number of "1's" in a given computer word. There are several techniques to implement bit-counting operation. These techniques are either software algorithms or specialized hardware techniques. The hardware implementations require dedicated hardware supported in the processor or associated math co-processor. The performance of the hardware-supported bit-counting was found to be superior to most software implementations (such as serial shifting). In this paper, a new hardware implementation of bit-counting routine is presented that reduces the number of logic gates and the delay in comparison with existing implementations. The performance of the proposed hardware bit-counting implementations is further investigated and evaluated.

Volume

5

Issue

7

First Page

1626

Last Page

1631

Disciplines

Computer Sciences

Keywords

Bit-Counting, Bit-Parallelism, Counters, Popcount, Redundant coding

Scopus ID

33745498253

Indexed in Scopus

yes

Open Access

no

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