New hardware architecture for bit-counting

Document Type

Conference Proceeding

Source of Publication

Proceedings of the 5th WSEAS International Conference on Applied Computer Science (ACOS'06)

Publication Date

4-16-2006

Abstract

Bit-counting implementations are used to count the number of 1s in a given computer word. There are several techniques to implement -counting operation. These techniques are either software algorithms or specialized hardware techniques. The hardware implementations require hardware supported in the processor or associated math co-processor. The performance hardware-supported bit-counting was found to be superior to most software implementations serial shifting). In this paper, a new hardware implementation of bit-counting routine is presented reduces the number of logic gates and the delay in comparison with existing implementations. performance of the proposed hardware bit-counting implementations is further investigated evaluated.

First Page

118

Last Page

128

Disciplines

Computer Sciences

Indexed in Scopus

no

Open Access

yes

Open Access Type

Bronze: This publication is openly available on the publisher’s website but without an open license

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